1. Technical Field
The present invention relates to a data storing method, and more particularly, relates to a data storing method for a rewritable non-volatile memory and a memory control circuit unit and a memory storage device using the method.
2. Description of Related Art
The growth of digital cameras, mobile phones, and MP3 players has been rapid in recent years. Consequently, the consumers' demand for storage media has increased tremendously. In recent years, a rewritable non-volatile memory has become an import part of the electronic industries because the rewritable non-volatile memory is capable of providing features such as data non-volatility, low power consumption, small volume, non-mechanical structure and high read/write speed. For instance, a solid-state drive utilizing a flash memory as a storage media has been widely applied in a computer host as a main hard disk for enhancing access efficiency of computer.
Data stored in the rewritable non-volatile memory may generate error bits due various factors (e.g., current leakage, programming failures and damages on the memory cell, and etc.). Therefore, an error checking and correcting circuit is generally disposed in a memory storage system to generate an error checking and correcting code for the stored data in order to ensure data correctness. However, when the number of the error bits exceeds the number of the error bits that can be detected and corrected by the error checking and correcting circuit, the data containing the error bits cannot be corrected to cause loss of data. Generally, in aforementioned condition, the data can still be corrected according to a parity that is stored in the rewritable non-volatile memory and corresponding to the data to be corrected. Traditionally, the data in a data bit area and a redundancy bit area of physical programming units where the parity is located is also calculated from other data under protections. Accordingly, information in the redundancy bit area cannot be used to ensure that the physical programming units are the physical programming units where the parity is located. Therefore, in a traditional method, the parity is placed at fixed positions.
For example, assuming that the memory storage system has eight memory dies, the last one among the memory dies can be used to store the parity. If the data from a host system only requires to be written into one physical programming unit, in order to generate the parity to be stored in the corresponding physical programming units of an eighth memory die, dummy data needs to be filled into the corresponding physical programming units in other six memory dies. In other words, this method results in waste of storage spaces in a memory storage device. Accordingly, it is one of the major subjects in the industry as how to avoid waste of the storage spaces in the memory storage device while improving correcting capability and performance in error collections.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.